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Cache hierarchy
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51	Lecture 10: Memory Hierarchy—3 Cs and 7 Ways to Reduce Misses Professor David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-02-26 13:05:55 Computing Cache CPU cache Alpha 21164 Dynamic random-access memory Memory hierarchy Computer architecture Computer memory Computer hardware Central processing unit
52	FPGA Implementation of a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis Katevenis, Dionisios Pne Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:59 CPU cache Scratchpad memory Direct memory access Cache Remote direct memory access AMD 10h Memory hierarchy Cell Synchronous dynamic random-access memory Computer memory Computer hardware Computing
53	Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis Katevenis, Dionisios Pnevmatikatos Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:59 Scratchpad memory CPU cache Remote direct memory access Direct memory access Cache Memory hierarchy Computer memory Computer hardware Computing
54	A run-time Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability George Nikiforos, George Kalokairinos, Vassilis Papaefstathiou, Stamatis Kavadias, Dionisis Pnevmatikatos and Manolis Katevenis Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:59 CPU cache Scratchpad memory Direct memory access Cache AMD 10h Memory hierarchy Cell Computer hardware Computer memory Computing
55	The Cache Performance of Blocked Monica S. Lam, Add to Reading List Source URL: www-suif.stanford.edu Language: English - Date: 2003-10-16 22:29:20 Computer hardware Compiler optimizations CPU cache Central processing unit Data Memory hierarchy Cache-oblivious algorithm Loop tiling Cache Computer memory Computing
56	Reinventing Scheduling for Multicore Systems Silas Boyd-Wickizer, Robert Morris, M. Frans Kaashoek (MIT) A BSTRACT cache in other cores, but if the application stays on one Add to Reading List Source URL: pdos.csail.mit.edu Language: English - Date: 2015-04-29 10:31:17 Microprocessors Central processing unit Computer memory Parallel computing CPU cache Multi-core processor Scheduling Thread Memory hierarchy Computing Computer hardware Computer architecture
57	PetascaleSoftware-new.pptx Add to Reading List Source URL: gladiator.ncsa.illinois.edu Language: English - Date: 2010-05-20 14:16:48 CPU cache Sizeof Petascale Memory hierarchy Sparse matrix Parallel computing Transmission Control Protocol Computing Computer memory Computer hardware
58	Design and Evaluation of a Compiler Algorithm for Prefetching Todd C. Mowry, Monica S. Lam and Anoop Gupta Computer Systems Laboratory Stanford University, CA 94305 Add to Reading List Source URL: www-suif.stanford.edu Language: English - Date: 2006-06-25 21:11:32 Computer hardware Computer programming CPU cache Loop nest optimization Cache Memory hierarchy Software pipelining Lookup table Acumem SlowSpotter Computing Computer memory Compiler optimizations
59	Staged Reads : Mitigating the Impact of DRAM Writes on DRAM Reads ∗ Niladrish Chatterjee University of Utah Naveen Muralimanohar Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2012-01-10 00:00:20 Dynamic random-access memory CPU cache Random-access memory Write buffer Memory controller CAS latency Memory hierarchy DDR3 SDRAM RLDRAM Computer memory Computer hardware Computing
60	Sandbox Prefetching: Safe Run-Time Evaluation of Aggressive Prefetchers Seth H Pugsley1 , Zeshan Chishti2 , Chris Wilkerson2 , Peng-fei Chuang3 , Robert L Scott3 , Aamer Jaleel4 , Shih-Lien Lu2 , Kingsum Chow3 , and Raje Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2014-01-10 15:51:59 Computer architecture Prefetcher CPU cache AMD 10h Memory hierarchy Cache NForce Lookup table Acumem SlowSpotter Computer hardware Computing Computer memory